The invention relates generally to semiconductor circuitry, and more specifically to a high voltage CMOS output driver in a low voltage semiconductor process.
While semiconductor circuitry such as bipolar and CMOS circuitry has traditionally operated at a five volt potential difference between a high and a low signal level, the need for higher speed, lower power consumption, and lower heat dissipation has prompted a move to lower voltage circuitry. It is now common for such semiconductors to operate at voltage levels of 3.3 or 2.5 volts, allowing fabrication of such higher performance semiconductor devices.
Although such devices are capable of a higher level of performance in many respects than older five volt semiconductors, they often must be integrated into designs or products utilizing the older five volt technology and so must be designed to interface with such circuitry. These lower voltage semiconductors are often designed to receive either a five volt signal or a lower voltage signal in the same device, making integration into older systems relatively easy where the newer low voltage semiconductors must receive signals.
But, these lower voltage semiconductors cannot provide a five volt output signal as easily as the can receive one. Because the fabrication processes used in these lower voltage semiconductors comprise standard transistor geometries designed to conduct only lower voltages, they are not physically capable of reliably providing a full five volt output signal.
What is desired is a high voltage output driver capable of providing a high voltage output signal in a low voltage process semiconductor.
The invention described here provides a high-voltage output buffer implemented in a low-voltage semiconductor process, enabling low-voltage semiconductors to interface with high-voltage circuitry. The buffer comprises a level translator circuit that in operation receives a signal varying between ground and a low voltage level, and outputs a corresponding signal varying between a reference voltage level and a high voltage level. The reference voltage level is an intermediate voltage level between half of the low voltage level and the high voltage level. The buffer also comprises an output circuit that in operation receives the output of the level translator circuit, and outputs a corresponding high voltage level when the input is a high voltage level or a zero voltage level when the input is at the reference voltage level. The low voltage supply in some embodiments of the invention is derived from the greater of an external low voltage supply or the reference voltage derived from the high voltage supply, so that the transistors of the buffer are protected from high voltages in the event of an external low voltage supply failure.